1Field of the Invention
The present invention relates to switching devices for flat displays, and more particularly to polysilicon thin film transistors applied to liquid crystal displays.
2. Description of the Prior Art
Polysilicon thin film transistors (TFTs) have a polysilicon semiconductor layer serving as a conduction passage between a source and a drain and control current flowing between the source and drain to serve as switches.
Recently, liquid crystal displays (LCDs) have made rapid progresses as new type flat dispiays. In particular, in cases of LCDs of a dot matrix displaying type in which a TFT is provided at each pixel, for displaying a large character or picture, amorphous silicon TFTs have been used as switching devices, so as to obtain a better quality of LCD image.
For displaying such a large character, however, the pixel density of LCD should be increased. Such an increase in pixel density results in an increase in the density of wires connected to drive circuits. For solving these problems, there has been a proposal of forming both LCD drive circuit and switching device on a glass substrate or a quartz substrate, by using polysilicon TFT having a high electron mobility.
Where the quartz substrates are used, the polysilicon thin films can be treated at a high temperature of not less than 600.degree. C. In the case of using the glass substrates, however, the treating temperature is limited to a level of less than 600.degree. C. The polysilicon thin films of TFTs can be manufactured not only by using a low pressure chemical vapor deposition (LPCVD) method, but also by depositing an amorphous silicon layer and then heat treating the amorphous silicon layer using a laser annealing method or other similar method. Otherwise, the polysilicon thin films may be made without any heat treatment, by using a special deposition method.
Referring to FIG. 1, there is illustrated an example of a conventional staggered polysilicon TFT.
As shown in FIG. 1, the conventional polysilicon TFT comprises an insulating substrate 11 having a channel region 12', source/drain regions 15 disposed at opposite sides of the channel region 12', a gate region disposed over the channel region 12' and isolated from the channel region 12' by a gate insulating film 13, contacts 17 and 18 disposed over the channel region 12' and the source/drain regions 15, respectively, a gate electrode 19 disposed above the channel region 12' and isolated from the channel region 12' by an insulating film 16, and source/drain electrodes 20 disposed over the source/drain regions 15 and isolated from the gate electrode by insulating films 13 and 16. The gate electrode 19 and the source/drain electrodes 20 are connected with the gate region 14 and the source/drain regions 15 by the contacts 17 and 18, respectively.
FIGS. 2a to 2e are schematic sectional views illustrating a method of making the polysilicon TFT with the conventional structure shown in FIG. 1.
In accordance with the method, first, a undoped polysilicon film 12 is deposited over the insulating substrate 11, using the LPCVD method, as shown in FIG. 2a. Thereafter, the polysilicon film 12 is subjected to a patterning using photolithography, so as to remove its unnecessary portion and thus form a pattern.
Over the resultant. entire exposed surface, the gate insulating film 13 is deposited using the LPCVD method, the plasma enhanced chemical vapor deposition (PECVD) method or the ECR method, to have a thickness of 1000 .ANG. to 4,000 .ANG., as shown in FIG. 2b. Over the gate insulating film 13 is then deposited a phosphorous-doped polysilicon film which is, in turn, subjected to a patterning using a photoetching process, so as to form the gate region 14.
Using the gate region 14 as a mask, phosphorous (P) ions are implanted in the undoped polysilicon film 12 so that the source/drain regions 15 are formed in a self-aligned manner. At this time, the undoped portion of polysilicon film 12 disposed beneath the gate region 14 and between the source/drain-regions 15 forms the channel region 12'.
As shown in FIG. 2c, an insulating film 16 is then deposited over the resultant entire exposed surface. The insulating film 16 is subjected to a photoetching, so as to remove portions of insulating films 13 and 16 disposed over the gate region 14 and the source drain regions 15 and thus a form the contacts 17 and 18.
Finally, the gate metal electrode 19 and the source/drain metal electrodes 20 are formed over the contacts 17 and 18 such that they are in contact with the gate region 14 and the source/drain regions 15, respectively.
For making CMOS type TFTs, however, the conventional method should also comprise an ion implantation process involving at least two steps of implanting n type ions and implanting p type ions. Even in a doped polysilicon layer, its serial resistance is increased, since its thickness becomes thinner.
Accordingly, the conventional method also involves an ion implantation for additionally implanting a large quantity of ions in source/drain regions. As the number of ion implantation steps is increased as mentioned above, the number of photomasking steps is also increased, thereby causing the yield of TFTs to be decreased.